Field of the Invention
The present invention relates to integrated circuits (ICs) and, more particularly, to an improved method of forming an integrated circuit (IC) structure with shallow trench isolation (STI) regions and the resulting IC structure.
Description of Related Art
More specifically, in conventional integrated circuit (IC) processing using semiconductor-on-insulator wafers (e.g., silicon-on-insulator (SOI) wafers), semiconductor mesas for device regions are defined by forming shallow trench isolation (STI) regions. Specifically, such processing begins with a semiconductor-on-insulator wafer, which includes a semiconductor substrate (e.g. a silicon substrate), an insulator layer (e.g., a buried oxide (BOX) layer) on the semiconductor substrate and a semiconductor layer (e.g., a silicon layer) on the insulator layer. The semiconductor layer is lithographically patterned and etched to form trenches, which extend vertically or nearly vertically through the semiconductor layer to or into the insulator layer and which laterally surround semiconductor mesas for device regions within the semiconductor layer. Isolation material (e.g., silicon oxide) is then deposited to fill the trenches and a planarizing process (e.g., a chemical mechanical polishing (CMP) process) is performed in order to remove the isolation material from the top surface of the semiconductor semiconductor mesas, thereby forming the STI regions. Semiconductor devices (e.g., field effect transistors (FETs), bipolar junction transistors (BJTs), diodes, etc.) are subsequently formed in the semiconductor mesas and the STI regions provide for electrical isolation. Unfortunately, IC processing that includes this type of STI formation can be costly and time consuming. Therefore, there is a need in the art for an improved method of forming an integrated circuit (IC) structure with shallow trench isolation (STI) regions.